1. Field of the Invention
The present disclosure relates to planarization materials for microelectronic and microelectromechanical electronics manufacture.
2. Description of Related Art
Advanced integrated circuit (IC) designs are highly dependent on complex device-layering techniques to produce semiconductor devices that are more powerful, have lower profiles, and require less energy to operate. To make these qualities possible, more circuits with much finer structures must be integrated into a microchip by constructing multiple layers of interconnects and dielectrics on a semiconductor substrate in an appropriate sequence. Currently, photolithography is the predominant technique used to pattern these ultrafine structures. This technique requires materials to be deposited and removed from the surface to construct such ultrafine structures.
Photolithography involves depositing a photosensitive material, usually a photoresist, onto a semiconductor substrate surface. An optical transparent object, known as the photomask or reticle, with pre-defined images of the structures to be built on the semiconductor surface is placed above the photoresist-coated substrate. An appropriate wavelength of light is then illuminated through the optical object. The light either decomposes or cures the exposed area of the photoresist, depending on the nature of the photoresist and the process. The semiconductor surface is then developed to produce the patterned image on the substrate surface, and the procedure is then repeated for additional layers.
Materials can be applied in a uniform thickness if the surface to be treated is entirely planar. However, if the surface is not planar, materials may not coat with a uniform thickness. For example, a coating deposited on top of a topographic surface tends to contour to the topography of the underlying surface, thus producing a conformal, non-planar surface. As more layers are built on the surface, the severity of the surface topography increases. Moreover, at some point of applying successive layers of structure to a non-uniform surface of an IC, the non-planar surface becomes unsuitable for constructing the next structural layer. Unfortunately, non-planar surfaces reduce the final yield and performance of IC devices. Therefore, the topographic surface of the IC must be planarized, or flattened, prior to the construction of the next layer. To planarize the topographic surface, techniques such as wet or dry etching, chemical mechanical polishing (CMP), and contact planarization (CP) can be used.
As the feature sizes of microelectronic structures shrink, planarization of the structures becomes increasingly difficult. The width of the structures decreases at a faster rate than the height, due to material and photolithography limitations. This causes the aspect ratio to increase. As the aspect ratio increases, it becomes more difficult to deposit planarization materials in the spaces between features and to create a non-conformal coating.
In addition to IC manufacture, emerging technology such as microelectromechanical systems (MEMS) increasingly requires planarization techniques. MEMS are constructed using many of the same methods as ICs, such as photolithography and etching steps, but the topographies created can be orders of magnitude greater than those of typical IC structures. Advanced MEMS and packaging applications require deep filling and planarization of a device having high-aspect-ratio (HAR) structures to support further integration.
A number of planarization materials and processing methods have been developed to address the current issues. Currently, thick photoresist is one of the materials being used to planarize extreme topography. However, photoresist is not inherently planarizing and will crosslink, making it difficult to remove cleanly. Benzocyclobutene (BCB), sold as Cyclotene® from Dow Chemical, is also being used to planarize topography. However, BCB is not spin-bowl compatible and requires a dedicated track system for coating and baking. It also contains mesitylene solvent, which is banned in some semiconductor laboratories. Dry films have also been explored to use as planarization materials. However, a need remains in the art for suitable planarizing materials and processes.